`timescale 1 ns / 100 ps

module TimerCoreLogic_tb;

	reg load_flag;
	reg [15:0] ResetVal;
	reg [15:0] LoadVal;
	reg ModeSel;
	reg clk;
	reg rst_n;
	reg StartStop;
	reg clk_50Mhz;

	wire [7:0] LSBbinaryout;
	wire [7:0] MSBbinaryout;

	TimerCoreLogic dut (
		.load_flag(load_flag),
		.ResetVal(ResetVal),
		.LoadVal(LoadVal),
		.ModeSel(ModeSel),
		.clk(clk),
		.rst_n(rst_n),
		.StartStop(StartStop),
		.clk_50Mhz(clk_50Mhz),
		.LSBbinaryout(LSBbinaryout),
		.MSBbinaryout(MSBbinaryout)
	);

	always #10 clk = ~clk;
	always #10 clk_50Mhz = ~clk_50Mhz;

	initial begin
		clk = 0;
		clk_50Mhz = 0;
		rst_n = 1;
		StartStop = 1;
		load_flag = 0;
		ModeSel = 0;
		ResetVal = 16'd5;
		LoadVal = 16'd8000;

		#20 rst_n = 0;
		#20 rst_n = 1;

		load_flag = 1;
		#20 load_flag = 0;
		#20;

		StartStop = 0;
		#20 StartStop = 1;
		#500;
		StartStop = 0;
		#20 StartStop = 1;

		#200 ModeSel = 1;
		#20 ResetVal = 16'd100;
		#20 rst_n = 0;
		#20 rst_n = 1;

		#20 StartStop = 0;
		#20 StartStop = 1;
		#1000;

		StartStop = 0;
		#20 StartStop = 1;
		ResetVal = 16'd0;
		rst_n = 0;
		#40 rst_n = 1;
		#100;

		$stop; 
	end

endmodule
